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1 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram ?2002, micron technology, inc. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs products and specifications discussed herein are subject to change by micron without notice. 2mb syncburst ? sram features ? fast clock and oe# access times single +3.3v +0.3v/-0.165v power supply (v dd ) separate +3.3v or +2.5v isolated output buffer supply (v dd q) snooze mode for reduced-power standby single-cycle deselect (pentium ? bsram-compatible) common data inputs and data outputs individual byte write control and global write three chip enables for simple depth expansion and address pipelining clock-controlled and registered addresses, data i/os and control signals internally self-timed write cycle burst control pin (interleaved or linear burst) automatic power-down for portable applications 100-pin tqfp package low capacitive bus loading x18, x32, and x36 options available options marking timing (access/cycle/mhz) 3.5ns/5ns/200 mhz -5 3.5ns/6ns/166 mhz -6 4.0ns/7.5ns/133 mhz -7.5 5ns/10ns/100 mhz -10 configurations 3.3v i/o 128k x 18 MT58L128L18P 64k x 32 mt58l64l32p 64k x 36 mt58l64l36p 2.5v i/o 128k x 18 mt58l128v18p 64k x 32 mt58l64v32p 64k x 36 mt58l64v36p package 100-pin tqfp t operating temperature range commercial (0c to +70c) none part number example: MT58L128L18Pt-10 MT58L128L18P, mt58l64l32p, mt58l64l36p; mt58l128v18p, mt58l64v32p, mt58l64v36p 3.3v v dd , 3.3v or 2.5v i/o, pipelined, single- cycle deselect general description the micron ? syncburst ? sram family employs high-speed, low-power cmos designs that are fabri- cated using an advanced cmos process. micron?s 2mb syncburst srams integrate a 128k x 18, 64k x 32, or 64k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (clk). the synchronous inputs include all addresses, all data inputs, active low chip enable (ce#), two additional chip enables for easy depth expansion (ce2, ce2#), burst control inputs (adsc#, adsp#, adv#), byte write enables (bwx#), and global write (gw#). asynchronous inputs include the output enable (oe#), clock (clk), and snooze enable (zz). there is also a burst mode pin (mode) that selects between interleaved and linear burst modes. the data-out (q), enabled by oe#, is also asynchronous. write cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. burst operation can be initiated with either address status processor (adsp#) or address status controller (adsc#) input pins. subsequent burst addresses can be internally generated as controlled by the burst advance pin (adv#). *jedec-standard ms-026 bha (lqfp). 100-pin tqfp*
2 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs functional block diagram 128k x 18 sa0, sa1, sa address register adv# clk binary counter and logic clr q1 q0 adsc# 17 17 15 17 bwb# bwa# ce# 18 byte ?b? write register byte ?a? write register enable register 18 sa0' sa1' oe# sense amps 128k x 9 x 2 memory array adsp# 9 9 2 sa0-sa1 mode ce2 ce2# gw# bwe# dqs dqpa dqpb 2 18 output registers 18 e 18 byte ?b? write driver byte ?a? write driver output buffers pipelined enable 9 9 input registers note: functional block diagrams illustrate simplified device operation. see truth table, pin descriptions, and timing diagrams for detailed information. address register adv# clk binary counter clr q1 q0 adsp# adsc# mode 16 16 14 16 bwd# bwc# bwe# gw# ce# ce2 ce2# oe# byte ?d? write register byte ?c? write register byte ?b? write register byte ?a? write register enable register dqs dqpa dqpb dqpc dqpd 4 output registers sense amps 64k x 8 x 4 (x32) 64k x 9 x 4 (x36) memory array 36 36 36 36 output buffers e byte ?a? write driver byte ?b? write driver byte ?c? write driver byte ?d? write driver pipelined enable input registers sa0, sa1, sa bwb# bwa# sa0' sa1' sa0-sa1 9 9 9 9 9 9 9 9 36 functional block diagram 64k x 32/36
3 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs general description (continued) address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during write cycles on the x18 device, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb. during write cycles on the x32 and x36 devices, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb; bwc# controls dqc pins and dqpc; bwd# controls dqd pins and dqpd. gw# low causes all bytes to be written. parity pins are only available on the x18 and x36 versions. this device incorporates a single-cycle deselect fea- ture during read cycles. if the device is immediately deselected after a read cycle, the output bus goes to a high-z state t kqhz nanoseconds after the rising edge of clock. micron?s 2mb syncburst srams operate from a +3.3v v dd power supply, and all inputs and outputs are ttl-compatible. users can choose either a 3.3v or 2.5v i/o version. the device is ideally suited for pentium and powerpc pipelined systems and systems that benefit from a very wide, high-speed data bus. the device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. please refer to micron?s web site ( www.micron.com/ sramds ) for the latest data sheet. *pin 50 is reserved for address expansion. **no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version. tqfp pin assignment table pin # x18 x32/x36 1 nc nc/ dqpc ** 2 nc dqc 3 nc dqc 4v dd q 5v ss 6nc dqc 7nc dqc 8 dqb dqc 9 dqb dqc 10 v ss 11 v dd q 12 dqb dqc 13 dqb dqc 14 v dd 15 v dd 16 nc 17 v ss 18 dqb dqd 19 dqb dqd 20 v dd q 21 v ss 22 dqb dqd 23 dqb dqd 24 dqpb dqd 25 nc dqd pin # x18 x32/x36 pin # x18 x32/x36 pin # x18 x32/x36 26 v ss 27 v dd q 28 nc dqd 29 nc dqd 30 nc nc/ dqpd ** 31 mode 32 sa 33 sa 34 sa 35 sa 36 sa1 37 sa0 38 dnu 39 dnu 40 v ss 41 v dd 42 dnu 43 dnu 44 sa 45 sa 46 sa 47 sa 48 sa 49 sa 50 nc/ sa * 76 v ss 77 v dd q 78 nc dqb 79 nc dqb 80 sa nc/dqpb** 81 sa 82 sa 83 adv# 84 adsp# 85 adsc# 86 oe# 87 bwe# 88 gw# 89 clk 90 v ss 91 v dd 92 ce2# 93 bwa# 94 bwb# 95 nc bwc# 96 nc bwd# 97 ce2 98 ce# 99 sa 100 sa 51 nc nc/ dqpa ** 52 nc dqa 53 nc dqa 54 v dd q 55 v ss 56 nc dqa 57 nc dqa 58 dqa 59 dqa 60 v ss 61 v dd q 62 dqa 63 dqa 64 zz 65 v dd 66 nc 67 v ss 68 dqa dqb 69 dqa dqb 70 v dd q 71 v ss 72 dqa dqb 73 dqa dqb 74 dqpa dqb 75 nc dqb
4 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs pin assignment (top view) 100-pin tqfp sa sa adv# adsp# adsc# oe# bwe# gw# clk v ss v dd ce2# bwa# bwb# nc nc ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sa nc nc v dd q v ss nc dqpa dqa dqa v ss v dd q dqa dqa v ss nc v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc nc/ sa * sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb v dd v dd nc v ss dqb dqb v dd q v ss dqb dqb dqpb nc v ss v dd q nc nc nc x18 sa sa adv# adsp# adsc# oe# bwe# gw# clk v ss v dd ce2# bwa# bwb# bwc# bwd# ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 nc/ dqpb ** dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss nc v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa nc/ dqpa ** nc/ sa * sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode nc/ dqpc ** dqc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc v dd v dd nc v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd nc/ dqpd ** x32/x36 1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 *pin 50 is reserved for address expansion. **no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version.
5 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs tqfp pin descriptions x18 x32/x36 symbol type description 37 37 sa0 input synchronous address inputs: these inputs are registered and must 36 36 sa1 meet the setup and hold times around the rising edge of clk. 32-35, 44-49, 32-35, 44-49, sa 80-82, 99, 81, 82, 99, 100 100 93 93 bwa# input synchronous byte write enables: these active low inputs allow 94 94 bwb# individual bytes to be written and must meet the setup and hold ? 95 bwc# times around the rising edge of clk. a byte write enable is low ? 96 bwd# for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb. for the x32 and x36 versions, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb; bwc# controls dqc pins and dqpc; bwd# controls dqd pins and dqpd. parity is only available on the x18 and x36 versions. 87 87 bwe# input byte write enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. 88 88 gw# input global write: this active low input allows a full 18-, 32-, or 36-bit write to occur independent of the bwe# and bwx# lines and must meet the setup and hold times around the rising edge of clk. 89 89 clk input c lock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 98 98 ce# input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp#. ce# is sampled only when a new external address is loaded. 92 92 ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 97 97 ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. 86 86 oe# input output enable: this active low, asynchronous input enables the data i/o output drivers. 83 83 adv# input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a high on this pin effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv# must be high at the rising edge of the first clock after an adsp# cycle is initiated. 84 84 adsp# input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc#, but dependent upon ce#, ce2 and ce2#. adsp# is ignored if ce# is high. power- down state is entered if ce2 is low or ce2# is high. (continued)
6 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs tqfp pin descriptions (continued) x18 x32/x36 symbol type description 85 85 adsc# input synchronous address status controller: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read or write is performed using the new address if ce# is low. adsc# is also used to place the chip into power-down state when ce# is high. 31 31 mode input mode: this input selects the burst sequence. a low on this pin selects ?linear burst.? nc or high on this pin selects ?interleaved burst.? do not alter input state while device is operating. 64 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. (a) 58, 59, (a) 52, 53, dqa input/ sram data i/os: for the x18 version, byte ?a? is associated with 62, 63, 68, 69, 56-59, 62, 63 output dqa pins; byte ?b? is associated with dqb pins. for the x32 and x36 72, 73 versions, byte ?a? is associated with dqa pins; byte ?b? is (b) 8, 9, 12, (b) 68, 69, dqb associated with dqb pins; byte ?c? is associated with dqc pins; 13, 18, 19, 22, 72-75, 78, 79 byte ?d? is associated with dqd pins. input data must meet setup 23 and hold times around the rising edge of clk. (c) 2, 3, 6-9, dqc 12, 13 (d) 18, 19, dqd 22-25, 28, 29 74 51 nc/ dqpa nc/ no connect/parity data i/os: on the x32 version, these pins are no 24 80 nc/ dqpb i/o connect (nc). on the x18 version, byte ?a? parity is dqpa; byte ?b? ? 1 nc /dqpc parity is dqpb. on the x36 version, byte ?a? parity is dqpa; byte ? 30 nc/ dqpd ?b? parity is dqpb; byte ?c? parity is dqpc; byte ?d? parity is dqpd. 14, 15, 41, 65, 14, 15, 41, 65, v dd supply power supply: see dc electrical characteristics and operating 91 91 conditions for range. 4, 11, 20, 27, 4, 11, 20, 27, v dd q supply isolated output buffer supply: see dc electrical characteristics and 54, 61, 70, 77 54, 61, 70, 77 operating conditions for range. 5, 10, 17, 21, 5, 10, 17, 21, v ss supply ground: gnd. 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 38, 39, 42, 43 38, 39, 42, 43 dnu ? do not use: these signals may either be unconnected or wired to gnd to improve package heat dissipation. 1-3, 6, 7, 16, 16, 66 nc ? no connect: these signals are not internally connected and may be 25, 28-30, connected to ground to improve package heat dissipation. 51-53, 56, 57, 66, 75, 78, 79, 95, 96 50 50 nc/ sa ? no connect: this pin is reserved for address expansion.
7 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 function gw# bwe# bwa# bwb# read h h x x read h l h h write byte ?a? h l l h write byte ?b? h l h l write all bytes h l l l write all bytes l x x x partial truth table for write commands (x18) partial truth table for write commands (x32/x36) function gw# bwe# bwa# bwb# bwc# bwd# read h h x x x x read h l h h h h write byte ?a? h l l h h h write all bytes h l l l l l write all bytes l x x x x x note: using bwe# and bwa# through bwd#, any one or more bytes may be written.
8 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs note: 1. x means ?don?t care.? # means active low. h means logic high. l means logic low. 2. for write#, l means any one or more byte write enable signals (bwa#, bwb#, bwc# or bwd#) and bwe# are low or gw# is low. write# = h for all bwx#, bwe#, gw# high. 3. bwa# enables writes to dqa pins and dqpa. bwb# enables writes to dqb pins and dqpb. bwc# enables writes to dqc pins and dqpc. bwd# enables writes to dqd pins and dqpd. dqpa and dqpb are only available on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe# must be high before the input data setup time and held high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp# low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe# low or gw# low for the subsequent l-h edge of clk. refer to write timing diagram for clarification. truth table operation address ce# ce2# ce2 zz adsp# adsc# adv# write# oe# clk dq used deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d
9 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs absolute maximum ratings* voltage on v dd supply relative to v ss .................................. -0.5v to +4.6v voltage on v dd q supply relative to v ss .................................. -0.5v to +4.6v v in .............................................. -0.5v to v dd q + 0.5v storage temperature (plastic) ........... -55c to +150c junction temperature** ................................... +150c short circuit output current .......................... 100ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. **maximum junction temperature depends upon pack- age type, cycle time, loading, ambient temperature, and airflow. see micron technical note tn-05-14 for more information. 3.3v i/o dc electrical characteristics and operating conditions (0c t a +70c; v dd , v dd q = +3.3v +0.3v/-0.165v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd output high voltage i oh = -4.0ma v oh 2.4 ? v 1, 4 output low voltage i ol = 8.0ma v ol ? 0.4 v 1, 4 supply voltage v dd 3.135 3.6 v 1 isolated output buffer supply v dd q 3.135 3.6 v 1, 5 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2 for 3.3v i/o and figure 4 for 2.5v i/o. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be connected together for 3.3v i/o.
10 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2 for 3.3v i/o and figure 4 for 2.5v i/o. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be connected together for 3.3v i/o. 2.5v i/o dc electrical characteristics and operating conditions (0c t a +70c; v dd = +3.3v +0.3v/-0.165v; v dd q = +2.5v +0.4v/-0.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 ? v 1, 4 i oh = -1.0ma v oh 2.0 ? v 1, 4 output low voltage i ol = 2.0ma v ol ? 0.7 v 1, 4 i ol = 1.0ma v ol ? 0.4 v 1, 4 supply voltage v dd 3.135 3.6 v 1 isolated output buffer supply v dd q 2.375 2.9 v 1
11 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs note: 1. v dd q = +3.3v +0.3v/-0.165v for 3.3v i/o configuration; v dd q = +2.5v +0.4v/-0.125v for 2.5v i/o configuration. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ?device deselected? means device is in power-down mode as defined in the truth table. ?device selected? means device is active (not in power-down mode). 4. typical values are measured at 3.3v, 25c and 10ns cycle time. 5. this parameter is sampled. tqfp capacitance description conditions symbol typ max units notes control input capacitance t a = 25c; f = 1 mhz; c i 2.7 3.5 p f 5 input/output capacitance (dq) v dd = 3.3v c o 45pf5 address capacitance c a 2.5 3.5 p f 5 clock capacitance c ck 2.5 3.5 p f 5 i dd operating conditions and maximum limits (note 1) (0c t a +70c; v dd = +3.3v +0.3v/-0.165v unless otherwise noted) description conditions sym typ -5 -6 -7.5 -10 units notes power supply device selected; all inputs v il current: or v ih ; cycle time t kc (min); i dd 100 400 340 280 225 ma 2, 3, 4 operating v dd = max; outputs open power supply device selected; v dd = max; current: idle adsc#, adsp#, gw#, bwx#, adv# i dd 1 30 100 85 70 65 ma 2, 3, 4 v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 0.5 10 10 10 10 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 6 25252525 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adsc#, adsp#, gw#, bwx#, adv# i sb 4 30 100 85 70 65 ma 3, 4 v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) max
12 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs tqfp thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods ja 40 c/w 1 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. jc 8 c/w 1 (junction to top of case) note: 1. typical values are measured at 3.3v, 25c and 10ns cycle time.
13 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs electrical characteristics and recommended ac operating conditions (note 1) (0c t a +70c; v dd = +3.3v +0.3v/-0.165v) -5 -6 -7.5 -10 description symbol min max min max min max min max units notes clock clock cycle time t kc 5.0 6.0 7.5 10 ns clock frequency f kf 200 166 133 100 mhz clock high time t kh 1.6 1.7 1.9 3.2 ns 2 clock low time t kl 1.6 1.7 1.9 3.2 ns 2 output times clock to output valid t kq 3.5 3.5 4.0 5.0 ns clock to output invalid t kqx 1.0 1.5 1.5 1.5 ns 3 clock to output in low-z t kqlz 0 1.5 1.5 1.5 ns 3, 4, 5, 6 clock to output in high-z t kqhz 3.5 3.5 4.0 5.0 ns 3, 4, 5, 6 oe# to output valid t oeq 3.5 3.5 4.0 5.0 ns 7 oe# to output in low-z t oelz 0000ns3, 4, 5, 6 oe# to output in high-z t oehz 3.0 3.5 4.0 4.5 ns 3, 4, 5, 6 setup times address t as 1.5 1.5 1.5 2.2 ns 8, 9 address status (adsc#, adsp#) t adss 1.5 1.5 1.5 2.2 ns 8, 9 address advance (adv#) t aas 1.5 1.5 1.5 2.2 ns 8, 9 write signals t ws 1.5 1.5 1.5 2.2 ns 8, 9 (bwa#-bwd#, bwe#, gw#) data-in t ds 1.5 1.5 1.5 2.2 ns 8, 9 chip enables (ce#, ce2#, ce2) t ces 1.5 1.5 1.5 2.2 ns 8, 9 hold times address t ah 0.5 0.5 0.5 0.5 ns 8, 9 address status (adsc#, adsp#) t adsh 0.5 0.5 0.5 0.5 ns 8, 9 address advance (adv#) t aah 0.5 0.5 0.5 0.5 ns 8, 9 write signals t wh 0.5 0.5 0.5 0.5 ns 8, 9 (bwa#-bwd#, bwe#, gw#) data-in t dh 0.5 0.5 0.5 0.5 ns 8, 9 chip enables (ce#, ce2#, ce2) t ceh 0.5 0.5 0.5 0.5 ns 8, 9 note: 1. test conditions as specified with the output loading shown in figure 1 for 3.3v i/o (v dd q = +3.3v +0.3v/-0.165v) and figure 3 for 2.5v i/o (v dd q = +2.5v +0.4v/-0.125v) unless otherwise noted. 2. measured as high above v ih and low below v il . 3. this parameter is measured with the output loading shown in figure 2 for 3.3v i/o and figure 4 for 2.5v i/o. 4. this parameter is sampled. 5. transition is measured 500mv from steady state voltage. 6. refer to technical note tn-58-09, ?synchronous sram bus contention design considerations,? for a more thorough discussion on these parameters. 7. oe# is a ?don?t care? when a byte write enable is sampled low. 8. a write cycle is defined by at least one byte write enable low and adsp# high for the required setup and hold times. a read cycle is defined by all byte write enables high and adsc# or adv# low or adsp# low for the required setup and hold times. 9. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when either adsp# or adsc# is low and chip enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when either adsp# or adsc# is low to remain enabled.
14 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs q 50 ? v = 1.5v z = 50 ? o t figure 1 q 351 317 5pf +3.3v figure 2 3.3v i/o ac test conditions input pulse levels ................. v ih = (v dd /2.2) + 1.5v ................... v il = (v dd /2.2) - 1.5v input rise and fall times .................................... 1ns input timing reference levels ..................... v dd /2.2 output reference levels ........................... v dd q/2.2 output load ........................... see figures 1 and 2 load derating curves the micron 128k x 18, 64k x 32, and 64k x 36 syncburst sram timing is dependent upon the capaci- tive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. q 50 ? v = 1.25v z = 50 ? o t figure 3 q 225 ? 225 ? 5pf +2.5v figure 4 2.5v i/o ac test conditions input pulse levels ............. v ih = (v dd /2.64) + 1.25v ............... v il = (v dd /2.64) - 1.25v input rise and fall times .................................... 1ns input timing reference level s ................... v dd /2.64 output reference levels .............................. v dd q/2 output load ........................... see figures 3 and 4 3.3v i/o output load equivalents 2.5v i/o output load equivalents
15 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs snooze mode snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after the device enters snooze mode, all in- puts except zz become gated inputs and are ignored. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb 2 z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz v ih i sb 2z 10 ma zz active to input ignored t zz 2( t kc) ns 1 zz inactive to input sampled t rzz 2( t kc) ns 1 zz active to snooze current t zzi 2( t kc) ns 1 zz inactive to exit snooze current t rzzi 0 ns 1 note: 1. this parameter is sampled. snooze mode waveform t zz i supply clk zz t rzz all inputs (except zz) don?t care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only
16 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs read timing t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces gw#, bwe#, bwa#-bwd# q high-z t kqlz t kqx t kq adv# t oehz t kq single read burst read t oeq t oelz t kqhz adv# suspends burst. burst wraps around to its initial state. t aah t aas t wh t ws t adsh t adss q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 (note 1) deselect cycle. (note 3) (note 4) burst continued with new base address. don?t care undefined note: 1. q(a2) refers to output from address a2. q(a2 + 1) refers to output from the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe# does not cause q to be driven until after the following clock rising edge. 4. outputs are disabled within one clock cycle after deselect. -5 -6 -7.5 -10 symbol min max min max min max min max units t as 1.5 1.5 1.5 2.2 ns t adss 1.5 1.5 1.5 2.2 ns t aas 1.5 1.5 1.5 2.2 ns t ws 1.5 1.5 1.5 2.2 ns t ces 1.5 1.5 1.5 2.2 ns t ah 0.5 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 0.5 ns t aah 0.5 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 0.5 ns read timing parameters -5 -6 -7.5 -10 symbol min max min max min max min max units t kc 5.0 6.0 7.5 10 ns f kf 200 166 133 100 mhz t kh 1.6 1.7 1.9 3.2 ns t kl 1.6 1.7 1.9 3.2 ns t kq 3.5 3.5 4.0 5.0 ns t kqx 1.0 1.5 1.5 1.5 ns t kqlz 0 1.5 1.5 1.5 ns t kqhz 3.5 3.5 4.0 5.0 ns t oeq 3.5 3.5 4.0 5.0 ns t oelz 0000 ns t oehz 3.0 3.5 4.0 4.5 ns
17 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs write timing t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces bwe#, bwa#-bwd# q high-z adv# burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 d extended burst write d(a2 + 2) single write t adsh t adss t adsh t adss t oehz t aah t aas t wh t ws t dh t ds (note 3) (note 1) (note 4) gw# t wh t ws (note 5) byte write signals are ignored for first cycle when adsp# initiates burst. adsc# extends burst. adv# suspends burst. don?t care undefined note: 1. d(a2) refers to input for address a2. q(a2 + 1) refers to input for the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. oe# must be high before the input data setup and held high throughout the data hold time. this prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. adv# must be high to permit a write to the loaded address. 5. full-width write can be initiated by gw# low; or gw# high and bwe#, bwa# and bwb# low for x18 device; or gw# high and bwe#, bwa#-bwd# low for x32 and x36 devices. -5 -6 -7.5 -10 symbol min max min max min max min max units t ds 1.5 1.5 1.5 2.2 ns t ces 1.5 1.5 1.5 2.2 ns t ah 0.5 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 0.5 ns t aah 0.5 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 0.5 ns t dh 0.5 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 0.5 ns write timing parameters -5 -6 -7.5 -10 symbol min max min max min max min max units t kc 5.0 6.0 7.5 10 ns f kf 200 166 133 100 mhz t kh 1.6 1.7 1.9 3.2 ns t kl 1.6 1.7 1.9 3.2 ns t oehz 3.0 3.5 4.0 4.5 ns t as 1.5 1.5 1.5 2.2 ns t adss 1.5 1.5 1.5 2.2 ns t aas 1.5 1.5 1.5 2.2 ns t ws 1.5 1.5 1.5 2.2 ns
18 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs read/write timing t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a2 t ceh t ces bwe#, bwa#-bwd# (note 4) q high-z adv# single write d(a3) a4 a5 a6 d(a5) d(a6) d burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t wh t ws q(a4+3) t oehz t dh t ds t oelz (note 1) t kqlz t kq back-to-back writes a1 (note 5) don?t care undefined a3 note: 1. q(a4) refers to output from address a4. q(a4 + 1) refers to output from the next internal burst address following a4. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. the data bus (q) remains in high-z following a write cycle unless an adsp#, adsc# or adv# cycle is performed. 4. gw# is high. 5. back-to-back reads may be controlled by either adsp# or adsc#. t adss 1.5 1.5 1.5 2.2 ns t ws 1.5 1.5 1.5 2.2 ns t ds 1.5 1.5 1.5 2.2 ns t ces 1.5 1.5 1.5 2.2 ns t ah 0.5 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 0.5 ns t dh 0.5 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 0.5 ns -5 -6 -7.5 -10 symbol min max min max min max min max units read/write timing parameters -5 -6 -7.5 -10 symbol min max min max min max min max units t kc 5.0 6.0 7.5 10 ns f kf 200 166 133 100 mhz t kh 1.6 1.7 1.9 3.2 ns t kl 1.6 1.7 1.9 3.2 ns t kq 3.5 3.5 4.0 5.0 ns t kqlz 0 1.5 1.5 1.5 ns t oelz 0000 ns t oehz 3.0 3.5 4.0 4.5 ns t as 1.5 1.5 1.5 2.2 ns
19 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs 100-pin plastic tqfp (jedec lqfp) 14.00 0.10 1.40 0.05 16.00 0.20 0.10 +0.10 -0.05 0.15 +0.03 -0.02 22.10 +0.10 -0.20 0.32 +0.06 -0.10 20.10 0.10 0.65 typ 0.625 1.60 max detail a see detail a 0.60 0.15 1.00 typ gage plane 0.25 0.10 pin #1 id note: 1. all dimensions in millimeters max or typical here noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, syncburst, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. data sheet designations no marking: this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
20 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. MT58L128L18P_c.p65 ? rev. c, pub. 11/02 ?2002, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 pipelined, scd syncburst sram not recomended for new designs revision history added ?not recomended for new d esigns,? rev. c, pub. 11/02, final ........................ november/22/02 removed 165-pin fbga package, rev. 6/ 01 ........................................................................................ .......... june/7/01 removed fbga part marking guide, rev 8/00, final ........................................................................ august/22/00 changed fbga capacitance values, rev 8/00, final ............................................................................. au gust/7/00 c i ; typ 2.5pf from 4pf; max. 3.5pf from 5pf c o ; typ 4pf from 6pf; max. 5pf from 7pf c ck ; typ 2.5pf from 5pf; max. 3.5pf from 6pf removed it references, rev 7/00, final ......................................................................................... ............ july/14/00 added fbga part marking guide added revision history to datasheet removed it from part number example, rev 6/00, final ....................................................................... june /21/00 added # of datalines to the databus in x32/36 block diagram added note - ?preliminary package data? to fbga capacitance and thermal resistance tables changed heading on mechanical drawing from bga to fbga added 165-pin fbga package, rev 3/00, final .................................................................................... . march/3/00 added preliminary package data to diagram

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